Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP5825683
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enable easy formation of a good insulation layer on a layer of layered carbide-base materials.SOLUTION: In a semiconductor device manufacturing method, a gate insulation layer 105 composed of aluminium oxide is formed on a channel layer 102 in a gate electrode formation region 111 by atomic layer deposition of performing a cycle including formation of an aluminium layer and oxidation of the formed aluminium layer by using dimethylethylamine alane as a material gas of aluminium and HO as an oxidation gas.
Inventors:
Yuichi Harada
Virtue Mitsu Eisuke
Virtue Mitsu Eisuke
Application Number:
JP2012161322A
Publication Date:
December 02, 2015
Filing Date:
July 20, 2012
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
National University Corporation Tokyo Institute of Technology
National University Corporation Tokyo Institute of Technology
International Classes:
H01L21/336; H01L21/205; H01L21/316; H01L29/78; H01L29/786; H01L51/05
Domestic Patent References:
| JP2011211175A | ||||
| JP2002060944A | ||||
| JP2005529492A |
Foreign References:
| WO2010113518A1 | ||||
| WO2012017533A1 | ||||
| US20040045503 | ||||
| US20070045752 |
Other References:
Y.Xuan et al.,Atomic-layer-deposited nanostructures for graphene-based nanoelectronics, Applied Physics Letters,2008年 1月 7日,Volume 92, Issue 1,pp.013101
Attorney, Agent or Firm:
Masaki Yamakawa
Shigeki Yamakawa
Yuzo Koike
Shigeki Yamakawa
Yuzo Koike