Title:
オンチップルータ及びそれを用いたマルチコアシステム
Document Type and Number:
Japanese Patent JP5847887
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an on-chip router capable of shortening a header length of a packet and reducing latency in a multicore system adopting a source routing system, and the multicore system using the same.SOLUTION: The on-chip router of an embodiment includes a header analysis section having a plurality of hop field extraction sections provided correspondingly to respective buffers, and a header rewrite section. Each of the hop field extraction sections receives input of header information of a packet accumulated in the corresponding buffer, and extracts a hop field storing output port information indicating an output port to output the packet received through an input port from the plurality of hop fields storing the output port information. The header rewrite section rewrites the output port information of the hop field to be used for the transfer of the packet by the on-chip router of an output destination of the packet among the plurality of hop fields with decoded output port information.
Inventors:
Tohru Sano
Application Number:
JP2014124443A
Publication Date:
January 27, 2016
Filing Date:
June 17, 2014
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H04L12/721
Domestic Patent References:
| JP2005045681A |
Foreign References:
| WO2010137572A1 |
Attorney, Agent or Firm:
Hirohito Katsunuma
Takeshi Sekine
Akaoka Akira
Masashi Yoshida
Takeshi Sekine
Akaoka Akira
Masashi Yoshida