Title:
３レベルユニットインバータ
Document Type and Number:
Japanese Patent JP5891940
Kind Code:
B2
Abstract:
In aspects of the invention, each three-level inverter unit has an output current detector. The output from each detector is given to connection wires via a resistor, the connection wires connecting the inverter units. The voltage across the resistor is detected and the deviation, or increment, of the current value of the unit concerned from the average value is determined. The rising up edge of the ON pulses for the IGBT to be controlled is delayed, corresponding to the magnitude of the deviation. Thus, the output current is balanced between the inverter units.
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Inventors:
Isao Amano
Application Number:
JP2012113512A
Publication Date:
March 23, 2016
Filing Date:
May 17, 2012
Export Citation:
Assignee:
Fuji Electric Co., Ltd.
International Classes:
H02M7/493; H02M7/48; H02M7/487
Domestic Patent References:
| JP10094259A | ||||
| JP2011223666A | ||||
| JP4033573A | ||||
| JP57108688U |
Attorney, Agent or Firm:
Akira Sakamoto