Title:
半導体装置、寿命推定装置、寿命推定方法
Document Type and Number:
Japanese Patent JP5894515
Kind Code:
B2
Abstract:
According to one embodiment, a semiconductor device includes a circuit board, a plurality of semiconductor chips stacked above the circuit board, first and second bumps, third and fourth bumps, and first and second detection units. The first and second bumps are provided in either a gap between the circuit board and the semiconductor chip or a gap between the two semiconductor chips. The third and fourth bumps are provided in any of gaps other than the gap in which the first and second bumps are provided. The first detection unit is electrically connected to the first bump to detect damage of the first bump and to generate a first signal indicating the damage of the first bump. The second detection unit is electrically connected to the third bump to detect damage of the third bump and to generate a second signal indicating the damage of the third bump.
Inventors:
Yu Yamayori
Kenji Hirohata
Kenji Hirohata
Application Number:
JP2012218786A
Publication Date:
March 30, 2016
Filing Date:
September 28, 2012
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/60; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2010073795A | ||||
| JP2012049418A | ||||
| JP2011257272A | ||||
| JP2010147426A |
Foreign References:
| WO2011121725A1 |
Attorney, Agent or Firm:
Tetsuya Mikan
Takumi Hara
Masayuki Sunai
Takumi Hara
Masayuki Sunai
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