Title:
マルチレーンＰＣＩエクスプレスＩＯ相互接続に対するケーブル冗長性およびフェイルオーバのための方法、装置、およびコンピュータ・プログラム
Document Type and Number:
Japanese Patent JP5932287
Kind Code:
B2
Abstract:
Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.
Inventors:
Gregory M. Nordstrom
Jai Robert Herring
Patrick Allen Backland
William Alan Thompson
Jai Robert Herring
Patrick Allen Backland
William Alan Thompson
Application Number:
JP2011228823A
Publication Date:
June 08, 2016
Filing Date:
October 18, 2011
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
G06F13/14; G06F13/00
Domestic Patent References:
| JP2010108211A | ||||
| JP2010237839A | ||||
| JP2009169854A |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Tasaichi Tanae
Yoshihiro City
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