Title:
半導体装置
Document Type and Number:
Japanese Patent JP6429647
Kind Code:
B2
Abstract:
To improve reliability of signal transmission of an interposer which couples between semiconductor chips. A reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a first wiring layer of an interposer. Also, a reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a second wiring layer of the interposer. Further, the signal wiring and the signal wiring cross each other in plan view. The reference potential wirings of the first wiring layer, and the reference potential wirings of the second wiring layer are coupled to each other at the periphery of their crossing portion.
Inventors:
Shuichi Kariyazaki
Shirai Wataru
Ryuichi Oikawa
Kuboyama Kenichi
Shirai Wataru
Ryuichi Oikawa
Kuboyama Kenichi
Application Number:
JP2015012482A
Publication Date:
November 28, 2018
Filing Date:
January 26, 2015
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L25/04; H01L23/12; H01L23/32; H01L25/18
Domestic Patent References:
| JP2009059822A | ||||
| JP2001007458A |
Attorney, Agent or Firm:
Tsutsui International Patent Office