Title:
半導体素子、半導体素子の製造方法、および電子機器
Document Type and Number:
Japanese Patent JP6447512
Kind Code:
B2
Abstract:
The present disclosure relates to a semiconductor element, a manufacturing method of a semiconductor element, and an electronic apparatus, which enable suppression of crack occurrences and leaks. The present technology has a laminated structure including an insulating film having a CTE value between those of metal and Si and disposed under a metal wiring, and P—SiO (1 μm) having good coverage and disposed as a via inner insulating film in a TSV side wall portion. As the insulating film having a CTE that is in the middle between those of metal and Si, for example, SiOC is used with a thickness of 0.1 μm and 2 μm respectively in the via inner insulating film and a field top insulating film continuous to the via inner insulating film. The present disclosure can be applied to, for example, a solid-state imaging element used in an imaging device.
Inventors:
Naoto Sasaki
Application Number:
JP2015553478A
Publication Date:
January 09, 2019
Filing Date:
December 05, 2014
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H01L21/3205; H01L21/768; H01L23/522; H01L23/532
Domestic Patent References:
| JP2013165099A | ||||
| JP2012244100A | ||||
| JP2011082496A |
Foreign References:
| WO2011125935A1 |
Attorney, Agent or Firm:
Takashi Nishikawa
Yoshio Inamoto
Yoshio Inamoto
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