Title:
多層電子支持構造体の製作方法
Document Type and Number:
Japanese Patent JP6459107
Kind Code:
B2
Abstract:
A multilayer electronic support structure comprising at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one one non-cylindrical via post that couples said pair of adjacent feature layers through the dielectric material in a Z direction perpendicular to the X-Y plane; wherein said at least one non-cylindrical via post is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane.
Inventors:
Drool Full Witz
Application Number:
JP2012213707A
Publication Date:
January 30, 2019
Filing Date:
September 27, 2012
Export Citation:
Assignee:
Two High Access Semiconductor Company Limited
International Classes:
H01L23/12
Domestic Patent References:
| JP2005294660A | ||||
| JP200423037A | ||||
| JP2002208779A | ||||
| JP2001284799A |
Foreign References:
| US20070289127 |
Attorney, Agent or Firm:
▲吉▼川 俊雄