Title:
演算処理装置，情報処理装置，及び情報処理装置の制御方法
Document Type and Number:
Japanese Patent JP6481427
Kind Code:
B2
Abstract:
An arithmetic processing apparatus includes multiple selection circuits that are connected in series, wherein at least one selection circuit, the at least one selection circuit being served as a first selection circuit, includes a selection unit that selects a first input unit from two or more input units each receiving, from a source or a selection circuit in a previous stage, data and an identifier of a sender of the data; based on the two or more identifiers, and priority information indicating respective priorities for multiple sources connected to: a selection circuit upstream to the first selection circuit; and the first selection circuit; an update unit that updates, in the priority information, a priority for a first source indicated by a first identifier being received by the first input unit; and a transfer unit that transfers data and the first identifier passed through the first input unit, to a destination.
Inventors:
Yasuhiro Kitamura
Application Number:
JP2015046691A
Publication Date:
March 13, 2019
Filing Date:
March 10, 2015
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04L12/28; H04L45/60
Domestic Patent References:
| JP2011008658A | ||||
| JP2000305894A | ||||
| JP6268665A |
Foreign References:
| WO2010086906A1 | ||||
| US5446738 |
Attorney, Agent or Firm:
Yu Sanada
Masahisa Yamamoto
Masahisa Yamamoto