Title:
半導体装置
Document Type and Number:
Japanese Patent JP6488037
Kind Code:
B2
Abstract:
To provide a programmable logic device in which the number of elements per bit in a memory array can be reduced and with which power consumption or operation frequency can be estimated accurately at a testing stage. Provided is a programmable logic device including a plurality of programmable logic elements and a memory array which stores configuration data that determines logic operation executed in the plurality of programmable logic elements. The memory array includes a plurality of memory elements. The memory element includes a node which establishes electrical connection between the programmable logic element and the memory array, a switch for supplying charge whose amount is determined by the configuration data to the node, holding the charge in the node, or releasing the charge from the node, and a plurality of wirings. Capacitance is formed between the node and the wiring.
Inventors:
Yoshimoto Kurokawa
Application Number:
JP2018047445A
Publication Date:
March 20, 2019
Filing Date:
March 15, 2018
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/82; H01L21/8234; H01L27/06; H01L27/088; H01L29/786; H03K19/177
Domestic Patent References:
| JP553689A | ||||
| JP2011172214A | ||||
| JP2005269616A | ||||
| JP2010199498A | ||||
| JP2001077686A | ||||
| JP2011119675A |