Title:
ゲート駆動回路及びシフトレジスタ
Document Type and Number:
Japanese Patent JP6488388
Kind Code:
B2
Abstract:
The present invention discloses a gate drive circuit and a shift register. The gate drive circuit comprises a plurality of shift register circuits which are cascade connected, and each of the shift register circuits comprises a clock control transmission circuit and a NOR gate latch circuit, wherein the clock control transmission circuit is triggered by a first clock pulse of a clock signal to transmit a gate drive pulse of a former stage to the NOR gate latch circuit, and the NOR gate latch circuit performs latch, and the NOR gate latch circuit is further triggered by a second clock pulse following the first clock pulse to output the gate drive pulse. With the aforesaid arrangement, the gate drive circuit of the present invention is applicable to CMOS process, and the power consumption is low and the noise margin is wide.
Inventors:
Kure
Application Number:
JP2017534659A
Publication Date:
March 20, 2019
Filing Date:
January 12, 2015
Export Citation:
Assignee:
SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
International Classes:
G09G3/36; G09G3/20; G11C19/28; H03K3/037; H03K3/356
Domestic Patent References:
| JP11338439A | ||||
| JP6291640A |
Foreign References:
| CN103280176A | ||||
| US5825210 | ||||
| CN103345911A | ||||
| CN1767048A | ||||
| US20120139886 |
Attorney, Agent or Firm:
Yoneda Koichiro
Seishiro Suzuki
Seishiro Suzuki