Title:
変換装置および情報処理システム
Document Type and Number:
Japanese Patent JP6546133
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To accelerate a processing speed while suppressing resource consumption when executing a module generated by high-level synthesis after parallelizing it in an FPGA.SOLUTION: An input unit 111 accepts input of a program in which a function for acquiring input data, performing a prescribed process and outputting output data, the function including a parameter to be substituted by either a first value or a second value in a prescribed process and an instruction, is written in a prescribed programming language. When the instruction is a specific instruction, a conversion unit 112 converts the program to a module in which it is written in a prescribed hardware description language executable in an FPGA that a process based on program be executed, the module enabling a write of data to a buffer used at module execution time when the parameter is a first value and disabling a write of data to the buffer when the parameter is a second value.SELECTED DRAWING: Figure 1
Inventors:
Kaneko Hitoshi
Kudo Ichiro
Nishiyama Satoshi
Kudo Ichiro
Nishiyama Satoshi
Application Number:
JP2016159506A
Publication Date:
July 17, 2019
Filing Date:
August 16, 2016
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G06F17/50; G06F8/51; H01L21/82
Domestic Patent References:
| JP2010205084A | ||||
| JP8106476A |
Foreign References:
| US8001499 |
Attorney, Agent or Firm:
Sakai International Patent Office