Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP6568751
Kind Code:
B2
Abstract:
In a semiconductor substrate, a memory cell region in which a flash memory cell is formed is defined by an element isolation region. A floating gate electrode of the flash memory cell includes a protruding portion protruding toward an erase gate electrode so as to flare from a portion located immediately below a control gate electrode. Protruding portion includes an end face of a height corresponding to a thickness, and an inclined surface continuous with end face. Protruding portion faces erase gate electrode with a tunnel oxide film interposed therebetween.
Inventors:
Hiroaki Mizushima
Application Number:
JP2015168753A
Publication Date:
August 28, 2019
Filing Date:
August 28, 2015
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/336; H01L21/8234; H01L27/088; H01L27/11521; H01L27/11526; H01L29/788; H01L29/792
Domestic Patent References:
| JP2014522122A | ||||
| JP2014096421A | ||||
| JP2004247470A | ||||
| JP2015130438A |
Attorney, Agent or Firm:
Fukami patent office