Title:
データ処理回路及びエラー訂正方法
Document Type and Number:
Japanese Patent JP6600146
Kind Code:
B2
Abstract:
A data processing circuit includes an error processing circuit and a memory. Word data is configured by main body data to be divided into a plurality of partial words and redundant data. The redundant data is configured by error correction additional bits generated from the main body data on the basis of a predetermined error correction algorithm and the error correction additional bits include a plurality of parity bits corresponding to the partial words. The error processing circuit includes error correction circuit and parity check circuit into which the word data is input in parallel. The error correction circuit decides an error type by using the redundant data and corrects a correctable error. The parity check circuit performs a parity check on the basis of access-requested partial word and the corresponding parity bit.
Inventors:
Hayashi Banichi
Application Number:
JP2015066301A
Publication Date:
October 30, 2019
Filing Date:
March 27, 2015
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H03M13/19; G06F11/10; G06F11/14; H04L1/00
Domestic Patent References:
| JP10097471A | ||||
| JP56094597A | ||||
| JP2013070122A | ||||
| JP7146825A | ||||
| JP62125453A |
Attorney, Agent or Firm:
Ken Ieiri