Title:
インターフェース回路
Document Type and Number:
Japanese Patent JP6698855
Kind Code:
B2
Abstract:
An interface circuit serves to receive an input signal VIN having a high level defined as a high potential VIH and a low level defined as a low potential VIL, and output an output signal VOUT having a high level defined as a high potential VOH and a low level defined as a low potential VOL. The interface circuit includes a polarity controller configured to control the output signal VOUT to be in phase in level with the input signal VIN or to be reversed in polarity with respect to the input signal VIN, depending on whether the high potential VIH or the low potential VIL is a GND potential.
Inventors:
Takayuki Nakai
Application Number:
JP2018540249A
Publication Date:
May 27, 2020
Filing Date:
September 20, 2016
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H03K19/0175
Domestic Patent References:
| JP2010011226A | ||||
| JP2006197564A | ||||
| JP9046199A | ||||
| JP8065146A | ||||
| JP2002368599A |
Foreign References:
| US4728820 |
Attorney, Agent or Firm:
Fukami patent office