Title:
端子構造、半導体装置、電子装置及び端子の形成方法
Document Type and Number:
Japanese Patent JP6702108
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To suppress side etching caused by seed etching, and to prevent solder from being spilled even when a solder layer having a sufficient thickness for bonding is formed.SOLUTION: A terminal structure is configured to comprise: a Cu pillar 1; a solder layer 2 provided above the Cu pillar; and a cover layer 3 that has a lower portion 3X at least containing Ni and B and covering a lateral face of the Cu pillar, and an upper portion 3Y at least containing B and covering a lateral face of the solder layer.SELECTED DRAWING: Figure 1
Inventors:
Morita
Toshiya Akamatsu
Toshiya Akamatsu
Application Number:
JP2016179639A
Publication Date:
May 27, 2020
Filing Date:
September 14, 2016
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L21/60; C22C19/03
Domestic Patent References:
| JP2010045234A | ||||
| JP2006245289A | ||||
| JP2016006812A | ||||
| JP2015216344A |
Attorney, Agent or Firm:
Yu Sanada