Title:
半導体素子、半導体装置、及び製造方法
Document Type and Number:
Japanese Patent JP6721663
Kind Code:
B2
Abstract:
To provide a semiconductor element which allows adjustment of a barrier height φ, and allows a zero bias operation and antenna impedance matching for improvement of detection sensitivity of a high-frequency band RF electric signal; and provide a manufacturing method of the semiconductor element and a semiconductor device equipped with the semiconductor element.SOLUTION: In a semiconductor element according to a present embodiment, a concentration of InGaAs (n-type InGaAs layer 2) is intentionally increased beyond a range where "a change in a barrier height by bias" as mentioned above is prevented to a range to be deeply degenerate thereby to increase an electron Fermi level (E) from a band end of the InGaAs (n-type InGaAs layer 2) toward a band end of an InP (InP depletion layer 3).SELECTED DRAWING: Figure 2
Inventors:
Makoto Shimizu
Hiroki Ito
Tadao Ishibashi
Isamu Odaka
Hiroki Ito
Tadao Ishibashi
Isamu Odaka
Application Number:
JP2018221315A
Publication Date:
July 15, 2020
Filing Date:
November 27, 2018
Export Citation:
Assignee:
NTT Electronics Corporation
International Classes:
H01L29/861; H01L21/329; H01L29/868; H01L29/93; H01Q1/38
Domestic Patent References:
| JP2014519711A | ||||
| JP2006066770A | ||||
| JP2010062533A | ||||
| JP2011023480A | ||||
| JP2000164891A |
Other References:
S.R.Forrest and O.K.Kim,An n-In0.53Ga0.47As/n-InP rectifiers,J.Appl.Phys.,米国,American Instuitute of Physics,1981年,Vol.52,pp.5838-5842
Attorney, Agent or Firm:
Kenji Okada
Katsuhiro Imashita
Katsuhiro Imashita