Title:
半導体装置
Document Type and Number:
Japanese Patent JP6722986
Kind Code:
B2
Abstract:
A semiconductor device with a novel structure is provided. In the semiconductor device executing a pipeline processing, a first arithmetic unit and a second arithmetic unit are provided for an execution stage, and transistors for performing power gating for the respective arithmetic units are provided. Only the arithmetic unit that performs an arithmetic operation is supplied with power supply voltage. Thus, fine-grained power gating can be performed, so that the power consumption of the semiconductor device can be reduced. In each of the transistors for performing power gating, a channel formation region includes an oxide semiconductor; thus, a reduction in leakage current between power supply lines can be achieved. Furthermore, these transistors and transistors in the arithmetic units can be provided in different layers, and thus an increase in area overhead due to the additionally provided transistors can be prevented.
Inventors:
Takahiko Ishizu
Uesugi Wataru
Uesugi Wataru
Application Number:
JP2015130599A
Publication Date:
July 15, 2020
Filing Date:
June 30, 2015
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H03K17/687; H01L21/822; H01L27/04; H01L27/08; H01L29/786; H03K19/00; H03K19/096
Domestic Patent References:
| JP11149373A | ||||
| JP200860370A | ||||
| JP2014123185A | ||||
| JP20139297A | ||||
| JP2003167730A | ||||
| JP2010198128A | ||||
| JP2007299355A |
Foreign References:
| WO2008001461A1 |