Title:
厚さが均一な埋め込み誘電体層を有する構造を作成するためのプロセス
Document Type and Number:
Japanese Patent JP6725286
Kind Code:
B2
Abstract:
A process is used for fabricating a final structure comprising in succession a useful semiconductor layer, a dielectric layer and a carrier substrate. The process comprises providing an intermediate structure including an upper layer, the dielectric layer and the carrier substrate, and finishing the intermediate structure to form the final structure by performing a treatment nonuniformly modifying the thickness of the dielectric layer following a predetermined dissolution profile. The dielectric layer of the intermediate structure has a thickness profile complementary to the predetermined dissolution profile.
Inventors:
Carol david
Anne-Sophie Koch
Anne-Sophie Koch
Application Number:
JP2016066013A
Publication Date:
July 15, 2020
Filing Date:
March 29, 2016
Export Citation:
Assignee:
Soitec
International Classes:
H01L21/02; H01L21/324; H01L27/12
Domestic Patent References:
| JP2015170796A | ||||
| JP2011504655A |
Attorney, Agent or Firm:
Patent Business Corporation Tani/Abe Patent Office