Title:
半導体装置
Document Type and Number:
Japanese Patent JP6761882
Kind Code:
B2
Abstract:
To provide a semiconductor device having a novel configuration, in which a malfunction and power consumption are reduced. A data holding circuit which includes a flipflop including first and second latch circuits and a shadow register including a nonvolatile memory portion; and a control signal generation circuit which generates a first control signal supplied to the first latch circuit and a second control signal supplied to the second latch circuit are included. The shadow register is a circuit which controls data saving or data restoring between the first and second latch circuits on the basis of a saving control signal or a restore control signal. The control signal generation circuit is a circuit which generates the first and second control signals at L level in a period during which data is saved or restored, on the basis of a clock signal, the saving control signal, and the restore control signal.
Inventors:
Takashi Nakagawa
Takayuki Ikeda
Yoshimoto Kurokawa
Uzumasa Munehiro
Ken Aoki
Takayuki Ikeda
Yoshimoto Kurokawa
Uzumasa Munehiro
Ken Aoki
Application Number:
JP2019081662A
Publication Date:
September 30, 2020
Filing Date:
April 23, 2019
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H03K3/037; G06F1/10; H03K3/356
Domestic Patent References:
| JP200977060A | ||||
| JP2012170107A |
Foreign References:
| US20030085748 | ||||
| US20070188211 |