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Title:
半導体集積回路装置及びその製造方法
Document Type and Number:
Japanese Patent JP6762004
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To block the noise from a semiconductor element to prevent the influence on another semiconductor element in and out of an integrated circuit and the noise coming from another semiconductor element.SOLUTION: A semiconductor integrated circuit device according to the present invention includes a semiconductor substrate, a first electromagnetic noise blocking layer provided on the semiconductor substrate, a circuit block provided thereon, and a second electromagnetic noise blocking layer provided thereon. The circuit block includes a circuit element portion including at least a ground electrode and a power source potential electrode, and insulating layers formed above and below the circuit element portion. The first electromagnetic noise blocking layer and the second electromagnetic noise blocking layer are formed in connection to a ground potential. The circuit block including the insulating layers above and below is configured to be held between the first electromagnetic noise blocking layer and the second electromagnetic noise blocking layer.SELECTED DRAWING: Figure 1

Inventors:
Satoshi Matsumoto
Masako Hasegawa
Application Number:
JP2016048113A
Publication Date:
September 30, 2020
Filing Date:
March 11, 2016
Export Citation:
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Assignee:
Kyushu Institute of Technology
National Institute of Advanced Industrial Science and Technology
International Classes:
H01L21/822; H01L21/3205; H01L21/768; H01L23/00; H01L23/522; H01L27/04
Domestic Patent References:
JP2013102133A
JP58039030A
JP2010109351A
JP2009295954A
JP5895848A
JP2011233913A
JP2000269446A
JP2003338559A
Foreign References:
WO2011037003A1
WO2014126800A1
Attorney, Agent or Firm:
Hattori Koichi