Title:
積和演算装置
Document Type and Number:
Japanese Patent JP6789576
Kind Code:
B2
Abstract:
A multiply-accumulate operation apparatus is capable of sufficiently restraining a sneak current when employing a precharge method where the magnitude of an electric current flowing through an output line is detected. In a synapse operation section, memory cells storing respective synaptic connection weights are arranged in rows and columns. Output lines are connected to memory cells in the corresponding column, and input lines are connected to memory cells in the corresponding row. Each output line is precharged, and then its electric potential is decreased during the corresponding memory cells flow cell currents corresponding to their synaptic connection weights. A memory element of each memory cell includes a memory transistor, a drain side transistor, and a source side transistor connected in series, and is connected between the corresponding input and output line. The memory transistor stores a synaptic connection weight according to the amount of charge in a charge storage layer.
Inventors:
Kazumasa Yanagisawa
Hayashi Banichi
Toshifumi Noda
Yasuhiro Taniguchi
Kosuke Okuyama
Hayashi Banichi
Toshifumi Noda
Yasuhiro Taniguchi
Kosuke Okuyama
Application Number:
JP2018146297A
Publication Date:
November 25, 2020
Filing Date:
August 02, 2018
Export Citation:
Assignee:
Flowia Inc.
International Classes:
G06G7/60; G06G7/16
Foreign References:
| US20170228345 | ||||
| WO2016178392A1 |
Attorney, Agent or Firm:
Patent Business Corporation Drite International Patent Office