Title:
電荷をトラップするための層を含む半導体素子の製造方法
Document Type and Number:
Japanese Patent JP6799015
Kind Code:
B2
Abstract:
A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700° C. and 1,100° C., for a period of time of at least 15 seconds.
Inventors:
Brockard, Marcel
Capella, Luciana
Bertrand, Isabel
Colombet, Norbert
Capella, Luciana
Bertrand, Isabel
Colombet, Norbert
Application Number:
JP2017564055A
Publication Date:
December 09, 2020
Filing Date:
June 01, 2016
Export Citation:
Assignee:
Sowatech
International Classes:
H01L21/02; H01L21/26; H01L21/322; H01L27/12
Domestic Patent References:
| JP2006066913A | ||||
| JP2003297839A | ||||
| JP2013513234A | ||||
| JP2007507093A |
Attorney, Agent or Firm:
Koichi Kamata