Title:
柱状半導体装置と、その製造方法。
Document Type and Number:
Japanese Patent JP6799872
Kind Code:
B2
Abstract:
A SiO2 layer is disposed in the bottom portion of a Si pillar and on an i-layer substrate. A gate HfO2 layer 11b is disposed so as to surround the side surface of the Si pillar, and a gate TiN layer is disposed so as to surround the HfO2 layer. P+ layers are disposed that contain an acceptor impurity at a high concentration, serve as a source and a drain, and are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar. Thus, an SGT is formed on the i-layer substrate.
Inventors:
Fujio Masuoka
Nozomi Harada
Yoshiaki Kikuchi
Nozomi Harada
Yoshiaki Kikuchi
Application Number:
JP2019539305A
Publication Date:
December 16, 2020
Filing Date:
May 28, 2018
Export Citation:
Assignee:
Unisantis Electronics Singapore Pte Ltd.
International Classes:
H01L21/336; H01L29/78
Domestic Patent References:
| JP2011108895A | ||||
| JP2009246383A | ||||
| JP2017117962A |
Foreign References:
| US9640636 | ||||
| US9799751 | ||||
| WO2018033981A1 |
Attorney, Agent or Firm:
Shinichiro Tanaka
Hiroyuki Suda
Fumiaki Otsuka
Takaki Nishijima
Hiroshi Uesugi
Nobuhiko Suzuki
Hiroyuki Suda
Fumiaki Otsuka
Takaki Nishijima
Hiroshi Uesugi
Nobuhiko Suzuki