Title:
３Ｄ ＮＡＮＤメモリデバイスにおける垂直エッチング性能の改善のための、膜のプラズマ化学気相堆積
Document Type and Number:
Japanese Patent JP6820153
Kind Code:
B2
Abstract:
The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.
Inventors:
Ja, placket pee.
Kor, Allen
Han, Shin Hai
Kwon, Thomas Jungwon
Kim, Bok Hohen
Kill, Byung Hun
Kim, Ryuun
Kim, Sang Hyuk
Kor, Allen
Han, Shin Hai
Kwon, Thomas Jungwon
Kim, Bok Hohen
Kill, Byung Hun
Kim, Ryuun
Kim, Sang Hyuk
Application Number:
JP2016063410A
Publication Date:
January 27, 2021
Filing Date:
March 28, 2016
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
H01L27/11556; H01L21/316; H01L21/318; H01L21/336; H01L27/11582; H01L29/788; H01L29/792
Domestic Patent References:
| JP2012174961A | ||||
| JP2012151187A | ||||
| JP3036769A | ||||
| JP2016529740A |
Foreign References:
| US20140357064 | ||||
| WO2015035381A1 | ||||
| US20120211821 | ||||
| US20120184078 | ||||
| US20160307764 |
Attorney, Agent or Firm:
Sonoda/Kobayashi Patent Business Corporation