Title:
インターポーザー、半導体装置、インターポーザーの製造方法、半導体装置の製造方法
Document Type and Number:
Japanese Patent JP6828733
Kind Code:
B2
Abstract:
To provide an interposer having sufficient reliability by preventing peeling of a conductive layer pattern by thermal expansion and thermal contraction, a semiconductor device, a method for manufacturing the interposer, and a method for manufacturing the semiconductor device.SOLUTION: An interposer is formed of a base material having a through hole, an insulating resin layer which is laminated on the base material and is formed with a conductive via, and a wiring group laminated on the insulating resin layer, where an inorganic adhesive layer is formed only in the through hole, a conductive layer is formed on the inorganic adhesive layer, the conductive layer includes a conductive land which is electrically connected to the wiring group via the conductive via and is formed between the conductive layer and the conductive via, a thermal expansion ratio of the inorganic adhesive layer is larger than a thermal expansion ratio of the base material and is smaller than a thermal expansion ratio of the conductive layer, and an outer diameter of the land is the same as an inner diameter of the through hole.SELECTED DRAWING: Figure 1
Inventors:
Koji Imayoshi
Application Number:
JP2018241479A
Publication Date:
February 10, 2021
Filing Date:
December 25, 2018
Export Citation:
Assignee:
Toppan Printing Co., Ltd.
International Classes:
H01L23/12; H01L23/15; H05K1/11; H05K3/40; H05K3/42; H05K3/46
Domestic Patent References:
| JP2013521663A | ||||
| JP2013197993A | ||||
| JP2006060119A | ||||
| JP2004111915A | ||||
| JP2012114400A | ||||
| JP2002261204A |
Foreign References:
| WO2011109648A1 | ||||
| WO2003007370A1 | ||||
| US20040217455 |
Attorney, Agent or Firm:
Ichi Hirose
Toru Miyasaka
Toru Miyasaka