Title:
ＤＤＲバスを通じてＤＲＡＭ内のＥＣＣ情報を伝達するデータチップ
Document Type and Number:
Japanese Patent JP6858682
Kind Code:
B2
Abstract:
A memory controller is disclosed. The memory controller may include read circuitry to request a value at an address stored in a plurality of data chips, parity circuitry to calculate a parity from original data received from the plurality of the data chips, pollution pattern analysis circuitry to compare the parity with a plurality of pollution patterns programmed into the plurality of the data chips to identify a data chip with an error, and error correction circuitry to correct the error in the original data received from the identified data chip with the error.
Inventors:
Beef people
Zhang Maki Tian
Hiroshi Zheng
Kim Hyun
Song Yuan
Choi stone
Zhang Maki Tian
Hiroshi Zheng
Kim Hyun
Song Yuan
Choi stone
Application Number:
JP2017184897A
Publication Date:
April 14, 2021
Filing Date:
September 26, 2017
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G06F11/10; G11C11/407
Domestic Patent References:
| JP2011217182A |
Attorney, Agent or Firm:
Kyosei International Patent Office