Title:
信号検出回路、光受信器、親局装置および信号検出方法
Document Type and Number:
Japanese Patent JP6858922
Kind Code:
B2
Abstract:
A signal detection circuit includes: a first DC voltage remover that removes a DC voltage from an input differential signal; a limiting amplifier that adjusts an amplitude of the input differential signal; a reset signal generator that generates an internal reset signal on the basis of the input differential signal obtained after the amplitude is adjusted; a first bias voltage applying unit that generates a differential signal for detection by applying a bias voltage to the signal from which the DC voltage is removed; and a flip-flop circuit that generates a packet detection signal by holding a state indicating input of a packet signal on the basis of the differential signal for detection and releasing the holding on the basis of the internal reset signal. The reset signal generator includes: a differential single-phase conversion circuit; a voltage holding circuit; and a voltage comparison circuit.
Inventors:
Satoshi Yoshima
Hironori Kawanaka
Hironori Kawanaka
Application Number:
JP2020501989A
Publication Date:
April 14, 2021
Filing Date:
February 26, 2018
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H04B10/69
Domestic Patent References:
| JP2015088850A | ||||
| JP2016063345A | ||||
| JP2013255056A |
Foreign References:
| US20130108278 |
Attorney, Agent or Firm:
Jun Takamura