Title:
半導体装置
Document Type and Number:
Japanese Patent JP6882943
Kind Code:
B2
Abstract:
The present invention enables an unaligned access of a DMA controller to be dealt at the time of obtaining trace data. A DMA controller receives a DMA request and accesses a memory via a bus on a predetermined access unit basis in accordance with the received DMA request. When the DMA request indicates “read”, a trace interface outputs the data obtained from the memory by the DMA controller, a start address designated by the DMA request, and valid transfer size in the data obtained from the memory to a trace circuit. The trace circuit stores data of the amount of the valid transfer size from the start address designated by the DMA request in the data obtained from the memory into the trace buffer.
Inventors:
Keiichi Kuwahara
Takuya Mitsuhashi
Takuya Mitsuhashi
Application Number:
JP2017123242A
Publication Date:
June 02, 2021
Filing Date:
June 23, 2017
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G06F13/28; G06F11/34
Domestic Patent References:
| JP2017126217A | ||||
| JP2005258889A | ||||
| JP2002175196A |
Attorney, Agent or Firm:
Ken Ieiri