Title:
低電力スケジューリング
Document Type and Number:
Japanese Patent JP6908661
Kind Code:
B2
Abstract:
The disclosure relates in some aspects to an energy-aware architecture that supports a low power scheduling mode. For example, a media access control (MAC) architecture for a base station (e.g., an enhanced Node B) and associated access terminals (e.g., UEs) can take the power needs of the access terminals into account when scheduling the access terminals. In some aspects, an access terminal may support a particular frame structure for a low power mode. Accordingly, scheduling of the access terminal may include use of the particular frame structure during low power mode.
Inventors:
Peter Puy Lok Ann
Ting Huang Ji
Jin Jiang
Krishna Kiran Mukkavili
Joseph Vinamira Soriaga
John Edward Smy
Naga Bushan
Ting Huang Ji
Jin Jiang
Krishna Kiran Mukkavili
Joseph Vinamira Soriaga
John Edward Smy
Naga Bushan
Application Number:
JP2019160303A
Publication Date:
July 28, 2021
Filing Date:
September 03, 2019
Export Citation:
Assignee:
Qualcomm, Inc.
International Classes:
H04W52/02; H04W28/04
Domestic Patent References:
| JP2013192010A | ||||
| JP2013115466A | ||||
| JP2013520102A | ||||
| JP2006518125A | ||||
| JP2011109252A |
Foreign References:
| US20140018085 | ||||
| US20130242824 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Kuroda Shinpei
Kuroda Shinpei