Title:
記憶装置
Document Type and Number:
Japanese Patent JP6908663
Kind Code:
B2
Abstract:
The memory device includes a first logic element which is supplied with a first power supply voltage, and inverts a polarity of a potential of an input terminal to output the potential with the inverted polarity from an output terminal, a second logic element which is supplied with a second power supply voltage supplied through a different path from the first power supply voltage, and inverts a polarity of a potential of an input terminal to output the potential with the inverted polarity from an output terminal, a first memory circuit connected to the input terminal of the first logic element, and a second memory circuit connected to the input terminal of the second logic element. The input terminal and the output terminal of the first logic element are connected to the output terminal and the input terminal of the second logic element, respectively.
Inventors:
Jun Koyama
Application Number:
JP2019164308A
Publication Date:
July 28, 2021
Filing Date:
September 10, 2019
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G11C14/00
Domestic Patent References:
| JP1066899A | ||||
| JP2011142621A | ||||
| JP2000048576A | ||||
| JP4057291A | ||||
| JP2011151796A | ||||
| JP2011171723A | ||||
| JP2004118921A |