Title:
デジタルにオーバーサンプリングされるセンサシステムにおける時間遅延、装置及び方法
Document Type and Number:
Japanese Patent JP6909289
Kind Code:
B2
Abstract:
Systems and methods are described to time delay a signal output from an analog-to-digital converter (ADC). The ADC includes a digital sensor responsive to an analog field quantity. The digital sensor is configured to output an oversampled digital output signal at a sampling clock frequency. A time delay element is configured to receive as an input, the oversampled digital output signal and to output a time delayed oversampled digital output signal. A filter is configured to receive as an input the delayed oversampled digital output signal. The filter low pass filters and decimates to a lower sample rate the delayed oversampled digital output signal. An output includes a low pass filtered decimated delayed digital output signal, where the lower sample rate is less than the sampling clock frequency.
More Like This:
Inventors:
Dasheng Fan
Joseph Yong Kwon
Joseph Yong Kwon
Application Number:
JP2019526185A
Publication Date:
July 28, 2021
Filing Date:
January 31, 2017
Export Citation:
Assignee:
Copin Corporation
International Classes:
H03M3/02; H04B14/02
Domestic Patent References:
| JP2010122191A | ||||
| JP2000197180A | ||||
| JP2016042036A | ||||
| JP2007243931A | ||||
| JP2002300224A |
Foreign References:
| US5883822 | ||||
| US20150281836 | ||||
| US20110013488 |
Attorney, Agent or Firm:
Murai Koji
Takeki Nishio
Takeki Nishio