Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP6927138
Kind Code:
B2
Abstract:
To restrain a side portion of a trench from being damaged by ion implantation. A method for manufacturing a semiconductor device comprises a stacking process, an ion implantation process, a heat treatment process, a groove forming process, and a first electrode forming process. In the stacking process, a p-type semiconductor layer is stacked on a first n-type semiconductor layer. In the ion implantation process, an n-type impurity or a p-type impurity is ion-implanted into a position on a surface of the p-type semiconductor layer. The position is away from a position where a groove is to be formed. In the heat treatment process, heat treatment is performed to activate the ion-implanted impurity so as to form an implanted region and to diffuse a p-type impurity in the p-type semiconductor layer into the first n-type semiconductor layer located below the implanted region so as to form a p-type impurity diffused region. In the groove forming process, the groove that penetrates the p-type semiconductor layer and has a bottom portion located in the first n-type semiconductor layer is formed. In the first electrode forming process, the first electrode is formed on an insulation film on a surface of the groove.
Inventors:
Ueno Yukihisa
Shigeaki Tanaka
Junya Nishii
Toru Oka
Shigeaki Tanaka
Junya Nishii
Toru Oka
Application Number:
JP2018089202A
Publication Date:
August 25, 2021
Filing Date:
May 07, 2018
Export Citation:
Assignee:
Toyoda Gosei Co., Ltd.
International Classes:
H01L29/78; H01L21/336; H01L29/12
Domestic Patent References:
| JP2017174989A | ||||
| JP2017135174A |
Attorney, Agent or Firm:
Meisei International Patent Office