Title:
垂直メモリデバイス
Document Type and Number:
Japanese Patent JP7412451
Kind Code:
B2
Abstract:
In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.
Inventors:
John Jean
Wenshi Jou
Gillian Shea
Wenshi Jou
Gillian Shea
Application Number:
JP2021570493A
Publication Date:
January 12, 2024
Filing Date:
August 23, 2019
Export Citation:
Assignee:
Yangtze Memory Technologies Co.,Ltd.
International Classes:
H10B43/50; H01L21/336; H01L29/788; H01L29/792; H10B41/50
Domestic Patent References:
| JP2008258458A |
Foreign References:
| CN108550574A | ||||
| US20170345844 | ||||
| US20140191388 | ||||
| US20170141032 | ||||
| US20150228623 | ||||
| US20130161821 | ||||
| US20170200676 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Shinya Mihiro
Tatsuhiko Abe
Shinya Mihiro
Tatsuhiko Abe