Title:
プロセッサの最適スロットルのためのシステム、機器、及び方法
Document Type and Number:
Japanese Patent JP7416706
Kind Code:
B2
Abstract:
In one embodiment, a processor includes: a plurality of processing elements to perform operations; a power management agent (PMA) coupled to the plurality of processing elements to control power consumption of the plurality of processing elements; and a throttling circuit coupled to the PMA. The throttling circuit is to determine a throttling power level for the plurality of processing elements based at least in part on translation information communicated from the PMA. Other embodiments are described and claimed.
Inventors:
Nge, Chee Rim
Harmarding, The Second, James Gee.
Datta, Proney
Resh, Joshua
Harmarding, The Second, James Gee.
Datta, Proney
Resh, Joshua
Application Number:
JP2020549669A
Publication Date:
January 17, 2024
Filing Date:
April 02, 2019
Export Citation:
Assignee:
Intel Corporation
International Classes:
G06F15/78; G06F1/3206; G06F1/3212; G06F1/3237; G06F1/3287; G06F1/3296
Foreign References:
| US20170285703 | ||||
| US20140317425 | ||||
| US20160154591 | ||||
| US20170364132 |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Osamu Miyazaki
Tadahiko Ito
Osamu Miyazaki
Previous Patent: ５’キャップトリヌクレオチドまたはより高級のオリゴヌクレオチド化合...
Next Patent: 微生物セルロースからビスコースドープ（ＶＩＳＣＯＳＥ ＤＯＰＥ）を製...
Next Patent: 微生物セルロースからビスコースドープ（ＶＩＳＣＯＳＥ ＤＯＰＥ）を製...