Title:
半導体構造及びその製造方法
Document Type and Number:
Japanese Patent JP7416891
Kind Code:
B2
Abstract:
A semiconductor structure includes a substrate, a dielectric layer, a connection layer and wire layers. The dielectric layer is disposed on a surface of the substrate and includes vias showing the surface. The connection layer is disposed on the dielectric layer, a first connection portion of the connection layer is located in the vias and connected to the surface, a second connection portion of the connection layer is connected to the dielectric layer. A first ground portion of the ground metal layer is connected to the first connection portion of the connection layer, and a second ground portion of the ground metal layer is connected to the second connection portion of the connection layer. Each of the wire layers is disposed on the second connection portion of the connection layer, and the second ground portion is located between the adjacent wire layers.
Inventors:
Xie Keitang
Xu Yu Ming
Junting Guo
What Ronghua
Guo Zhiming
Xu Yu Ming
Junting Guo
What Ronghua
Guo Zhiming
Application Number:
JP2022173354A
Publication Date:
January 17, 2024
Filing Date:
October 28, 2022
Export Citation:
Assignee:
ki Japanese technology Mining Co., Ltd.
International Classes:
H01L21/822; H01L21/3205; H01L21/768; H01L23/522; H01L27/04; H05K3/46
Domestic Patent References:
| JP2010074027A | ||||
| JP2013251520A | ||||
| JP2007134359A |
Foreign References:
| US20190131245 | ||||
| CN111785700A | ||||
| KR20210061186A |
Attorney, Agent or Firm:
Patent Attorney Corporation Hattori International Patent Office