Japanese Patent JPH0225208

B2

A serdes device includes circuitry for loading or reading bit configurations into or out of strings of latches of variable length nk+r, where n is the number of bits in a byte, k is the number of whole bytes and r is the number of residual bits, with r being smaller than n. Under the control of a service processor (8), there is formed a ring comprised of the latches of the serializer/deserializer register (14), the latches of the string considered (3 or 4) and a selected number (n-r) of latches of an extension register (16). The bytes to be loaded are sequentially sent to register (14), starting with the byte that contains the residual bits, and n bits are shifted out after loading each successive byte, so that after k+1 shifts the desired configuration will be contained in the string. For reading the contents of a string (for example, string 3), n bits are shifted, register (14) is read out, then k shifts of n bits each are performed, with register (14) being read out after each shift.

GI GASUTON DEYUFUORESUTERU
MISHERU ANDORE RUKACHINSUKI
KUREMAN IUON HOARO
HOORU PIEERU UIARON

JP20724184A

June 01, 1990

October 04, 1984

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INTAANASHONARU BIJINESU MASHIINZU CORP

G06F11/22; G01R31/317; G01R31/3185; G01R31/319; G11C19/00; H03M9/00

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