Document Type and Number:
Japanese Patent JPH0262982
Kind Code:
B2
Abstract:
PURPOSE:To stably operate without avoiding the super-position of asynchronous write/read operation, by using a time required for parallel convertion of digital data transmitted for each bit serially. CONSTITUTION:By using a counter 20 calculating transmission clock for data serial-parallel conversion and periodic read/write instruction signal generating circuit obtained from the frequency division of a reference clock produced at another reference clock signal generating circuit 5, timing signals f, g, j are produced from a timing generation circuit such as an ROM7 programmed in advance by taking the counter outputs X0-X3 of the counter 20 and an instruction signal output h' as the address input, and the program written in the ROM7 is suitably selected, the operation having higher frequency is given priority among write/read operations so that the mutual operations are not overlapped, allowing to avoid malfunction due to delay of elements.
Inventors:
YOKOZAWA SEIICHI
Application Number:
JP14530080A
Publication Date:
December 27, 1990
Filing Date:
October 17, 1980
Export Citation:
Assignee:
PIONEER ELECTRONIC CORP
International Classes:
H03M9/00; G06F5/10; H04B14/04; H04J3/06; H04L7/00; H04L13/08
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