Document Type and Number:
Japanese Patent JPH0311036
Kind Code:
B2
Abstract:
A serial input/output device includes a CMOS shift register having a plurality of D-type flip-flops. A detection circuit is associated with the CMOS shift register in order to detect whether the transfer data exists in the CMOS shift register. A gate circuit is provided for applying a transfer clock signal to the CMOS shift register only when the transfer data exists in the CMOS shift register, thereby minimizing the power consumption.
Inventors:
KAMURO SETSUSHI
HIRANO TAKAAKI
OKADA MIKIRO
HIRANO TAKAAKI
OKADA MIKIRO
Application Number:
JP14425283A
Publication Date:
February 15, 1991
Filing Date:
August 05, 1983
Export Citation:
Assignee:
SHARP KK
International Classes:
G11C19/28; G11C7/10; G11C19/00; H03M9/00