Title:
【発明の名称】階層構造を有するキャッシュメモリシステムを含むマルチプロセッサシステム
Document Type and Number:
Japanese Patent JPH03505793
Kind Code:
A
Abstract:
This invention relates to a computer system having a scalable, multiprocessor architecture with a distributed physical memory that supports data with a shared memory. The location of a data item in the machine is completely decoupled from its address. In particular, there is no distinguished home location where a data item must normally reside. Instead, data migrate automatically to where needed, reducing access times and traffic. The computer system is comprised of a hierarchy of buses and controllers linking an arbitrary number of processors, each with a large, set-associative memory. Each controller has a set-associative directory containing data for the data items under its control. The controllers process remote access of data by snooping buses above and below them. Utilizing this data-access protocol allows automatic migration, duplication, and displacement of data while maintaining data coherency and without losing data from the system.
Inventors:
Eric Hägersten
Khalidi, Safe
Warren, David, H., Di.
Khalidi, Safe
Warren, David, H., Di.
Application Number:
JP50728489A
Publication Date:
December 12, 1991
Filing Date:
June 29, 1989
Export Citation:
Assignee:
Swedish Institute of Computer Science
International Classes:
G06F12/02; G06F12/08; G06F12/0813; G06F12/0817; G06F15/16; G06F12/0831; (IPC1-7): G06F12/08
Attorney, Agent or Firm:
Kenmi Niimi (1 person outside)