Document Type and Number:
Japanese Patent JPH0445857
Kind Code:
B2
Abstract:
A 32-bit adder utilizes an optimal partitioning scheme for improving the 32-bit carry look-ahead. Instead of relying on the powers-of-four partitioning scheme used in prior art adders, the inventive technique uses "double generate" and "double propagate" terms. These represent the generate and propagate functions for two bits. In addition, "double group geneate" and "double group propagate" terms are produced, which represent the generate and propagate terms for a 8-bit groups. In this manner, a partition of 1-bit/8-bit is obtained, rather than the prior art 1-bit/4-bit/16-bit. The critical path is typically shortened from 7 logic levels to 5 logic levels, resulting in faster operation. The double functions are advantageously implemented using logic circuitry having two (or more) outputs per gate.
Inventors:
INSEOTSUKU SUCHIIUN FUWAN
Application Number:
JP3517689A
Publication Date:
July 28, 1992
Filing Date:
February 16, 1989
Export Citation:
Assignee:
AMERIKAN TEREFUON ANDO TEREGURAFU CO
International Classes:
G06F7/50; H03K21/00; G06F7/508; H03K23/00