Document Type and Number:
Japanese Patent JPH0457125
Kind Code:
B2
Abstract:
An operational amplifier gain stage utilizing switched capacitor resistor equivalent circuits is designed utilizing a delayed clock reference signal ( phi D, phi D) in a unique manner, thereby eliminating the effects of spurious error voltages (ES) generated when utilizing metal oxide silicon field effect transistors as switches (12, 15, 21, 23, 25). The single remaining MOSFET switch (21) which will contribute a spurious voltage component to the output of the operational amplifier gain stage is designed in such a manner as to minimize the spurious voltage generated during operation of the MOSFET switch. A single dummy switch (31) is utilized to further minimize the spurious voltage generated by this single MOSFET switch.
Inventors:
GIDEON AMIIRU
YUSUFU HEIKU
RUUBITSUKU GUREGORIAN
YUSUFU HEIKU
RUUBITSUKU GUREGORIAN
Application Number:
JP3252082A
Publication Date:
September 10, 1992
Filing Date:
March 03, 1982
Export Citation:
Assignee:
ASAHI KASEI MAIKURO SHISUTEMU KK
International Classes:
H03F3/70; G11C27/02; H01L21/339; H01L29/762; H03F1/30; H03F3/34; H03F99/00; H03H19/00; H03K17/00
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