Japanese Patent JPH0462203

B2

1. Modulator circuit realized as a switched capacitor (SC) filter, which is driven by a modulation clock (vphi M , ~v~p~h~i M ), comprising switches, capacitors and at least one operational amplifier (3) whose non-inverting input (5) is connected to a reference potential (1'), and in which an SC integrator driven by two different clock phases (vphi, ~v~p~h~i) is formed with the operational amplifier (3), and in which there is furthermore upstream of the inverting input (5) of the operational amplifier (3) an SC network which consists of a capacitor (6) which is charged during the integrator or network clock phase (vphi), and which delivers its charge during the modulation clock phases (vphi M or ~v~p~h~i M ) with opposite signs to the integration capacitor (7) associated with the operational amplifier (3), characterized in that the capacitor (6) to be charged during the integrator or network clock phase (vphi) is connected downstream of the input terminal (1, 1'), with intermediate connection of series arm and shunt arm switches (13, 14), in that following this capacitor (6) is a switch network (15, 16, 17, 18) which delivers the network clock phases (vphi and ~v~p~h~i) in an alternating manner in the rhythm of the modulation clock (vphi M and ~v~p~h~i M ) to a shunt arm switch (9) and series arm switch (10) respectively, and in that the series arm switch (10) is connected to the inverting input of the operational amplifier, in that provided in the filter output is a switch (11) which is followed by the output terminals (2, 1'), and in that the integration capacitor (7) and an attenuation capacitor (8) are switched between the output (23) and the inverting input (5) of the operational amplifier (3).

HERUMAN BETSUTSURU
YOOZEFU AA NOSEKU

JP5246784A

October 05, 1992

March 21, 1984

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SIEMENS AG

H03C5/00; H03C1/00; H03H19/00

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