Document Type and Number:
Japanese Patent JPH0516773
Kind Code:
B2
Abstract:
A working on the zero IF principle is disclosed which contains a feedback circuit instead of a preselector for suppressing interfering signals. The interfering signals contained in the incoming signal (FE) are separated from the useful signal by filters in the baseband. They are then reconverted to the RF value, amplified, and substracted from the incoming signal (FE) by a subtracter (S1). In the steady state, the output of the subtracter (S1) provides the useful signal, which is converted into the baseband and then fed to a signal processor (SV).
Inventors:
DEIITAA ROOTAA
DEIITAA BIIHIERUTO
MANFUREETO MOSUTAA
DEIITAA BIIHIERUTO
MANFUREETO MOSUTAA
Application Number:
JP10396986A
Publication Date:
March 05, 1993
Filing Date:
May 08, 1986
Export Citation:
Assignee:
ALCATEL NV
International Classes:
H04B1/10; H03D3/00; H03H19/00; H04B1/30; H03D7/16
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