Document Type and Number:
Japanese Patent JPH0550892
Kind Code:
B2
Abstract:
PURPOSE:To prevent momentary power supply fluctuation and malfunction due to induced noise generated at the transient output signal level change by providing plural delay circuits so as to correspond the current amplification factor of a transistor (TR) corresponding to a delay. CONSTITUTION:Delay circuits 10a-10n are connected to the 1st circuit 1 and the timing of the descending step from a high to a low level is made the same in its output waveform. Further, the delay quantity is changed little by little by changing the timing of the rising step from a low to a high level. Further, delay circuits 11a-11n are connected to the 2nd circuit 5, the timing of the rising step from a high to a low level is shifted little by little and the descending step from a low to a high level is made the same in the output waveform. In connecting the circuits 10a-10n and the circuits 11a-11n so that the long/ short delay corresponds depending on the large/small current amplification factor of the TR, momentary power supply fluctuation and malfunction due to induced noise are prevented.
Inventors:
KANEUCHI SHUJI
Application Number:
JP19070585A
Publication Date:
July 30, 1993
Filing Date:
August 28, 1985
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/8234; H01L27/08; H01L27/088; H03K4/00; H03K4/02; H03K17/16; H03K19/003; H03K19/0175; (IPC1-7): H03K19/0175; H03K17/16; H03K19/003
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