Document Type and Number:
Japanese Patent JPH0566680
Kind Code:
B2
Abstract:
An integrated circuit memory device such as E<2>PROM is provided with a circuit for generating a linear ramp voltage between 5 volts (Vcc) and 21 volts (Vpp) with a ramp rate of 16 volts/millisecond. A programming inhibit mode is provided during which an internal node corresponding to internal voltage Vpp is held at voltage Vcc by a transistor gate. A programming mode is also provided wherein an external programming voltage is integrated across a MOS capacitor T5. The programming voltage rise across the capacitor is maintained at 16 volts/millisecond by operating a transistor switch T6 to drop excessive external programming voltage to circuit ground in response to an excess voltage rise produced across the capacitor.
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Inventors:
ERUROI EMU RUSERO
Application Number:
JP17916184A
Publication Date:
September 22, 1993
Filing Date:
August 28, 1984
Export Citation:
Assignee:
NAT SEMICONDUCTOR CORP
International Classes:
H01L27/10; G05F3/24; G11C16/06; G11C16/12; G11C17/00; H01L21/8247; H01L27/06; H01L29/788; H01L29/792; H03K4/00; H03K19/003; (IPC1-7): G11C16/06
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