Japanese Patent JPH05872

B2

PURPOSE:To enable to satisfy three parameters for speed-up at the same time by providing a source-drain region of a semiconductor substrate with three or more different diffusion depths. CONSTITUTION:After forming an isolation oxide film 12 and a thermal oxide film 13 on the p type Si substrate 11, a gate oxide film 14 and a gate poly Si 15 of an MOS transistor are formed thereon, and the n-source-drain region 16 are formed over the entire surface of the p type Si substrate 11 after forming the gate poly Si 15. Next, a resist film is left only at a region to be desired to form the n-source-drain region, and As is implanted, thus forming the n<+> source- drain region 17 of deeper diffusion depth than that those of the n-source-drain region 16 are formed. The thermal oxide film 13 on the p type Si substrate 11 is locally removed, and a CVD oxide film 18 doped with phosphorus is adhered thereon. At this time, the phosphorus is diffused into the p type Si substrate 11 much more than at the part wherefrom the thermal oxide film 13 is removed, and thus an n<++> region 19 is formed. Then, contact holes are bored through the CVD oxide film 18, and a diffused region 20 of deep xj by diffusing phosphorus through the bored holes.

NAGAYAMA YASUHARU

JP20707682A

January 06, 1993

November 24, 1982

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MITSUBISHI ELECTRIC CORP

H01L27/10; H01L29/08; H01L29/78

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