Title:
【発明の名称】メモリ
Document Type and Number:
Japanese Patent JPH07101555
Kind Code:
B2
Abstract:
An improved integrated memory having row address inputs connected to a row address decoder and column address inputs connected to a column address decoder, the row address decoder and column address decoder having an address bus connected thereto, the memory being organized into an array of word lines (24) organized into rows and columns having a pair of bit lines (BLT, BLC) for each column, the improvement comprising, segmenting the array into a plurality of segments, each segment containing a portion of all of the bit lines; a bit equalization circuit for each said section, to equalize the potential on each bit line in the bit line pair when activated; an equalization circuit control means, having an input coupled to said input address lines, and an output connected to each equalization circuit on each respective segment of the array, for enabling the equalization circuits on those segments of the array which are not selected by the input address and for disabling the equalization circuits on that segment of the array which is selected by the input address; the bit line pairs in the non-selected circuits being maintained in an equal potential state so that when one of the bit lines in a bit line pair in a non-selected segment suffers a discharge due to an ionizing radiation effect, the activated equalization circuit on the non-selected segment will equalize the potential thereof; whereby the radiation immunity of the memory array is improved. The resulting memory array has enhanced radiation hardness, reduced power dissipation, and is capable of static page mode operation.
Inventors:
Michael Kevin Shirora
Christopher McCall Darhan
Reginald Erick Harrison
Darwin El Jallis
Dave Krytofar Lawson
Craig Lee Stephen
Christopher McCall Darhan
Reginald Erick Harrison
Darwin El Jallis
Dave Krytofar Lawson
Craig Lee Stephen
Application Number:
JP16007090A
Publication Date:
November 01, 1995
Filing Date:
June 20, 1990
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
G11C11/41; G11C5/00; G11C7/12; G11C7/18; G11C8/14; G11C11/401; G11C11/407; (IPC1-7): G11C11/41
Domestic Patent References:
| JP6258487A |
Attorney, Agent or Firm:
Kiyoshi Goda (2 outside)