Title:
【発明の名称】スタティック相補型半導体集積回路
Document Type and Number:
Japanese Patent JPH07101843
Kind Code:
B2
Abstract:
PURPOSE:To minimize the dislocation of the logical gate circuit change voltage of a static complementary semiconductor integrated circuit and to reduce an area by setting the gate width of the (n) pcs. of serial transistors from a conventional (n)-fold to n/2-fold or below. CONSTITUTION:In the circuit of 4 input NAND gates, the gate width of a P channel transistor 1 of an inverter circuit (a) is WP, the gate width of an N channel transistor 2 is made into WN and the 1/2 of a change voltage supply voltage is obtained, N channel transistors 7-10 go to 4WN/2.2, the WN goes to 4 pieces serially and goes to 4XWN/2 or below. Since P channel transistors 3-6 cannot be serial, the WP is obtained. The change voltage goes to approximately 1/2 as much as the supply voltage.
Inventors:
Kazuki Ninomiya
Takashi Taniguchi
Tetsuya Tanaka
Takashi Taniguchi
Tetsuya Tanaka
Application Number:
JP18594688A
Publication Date:
November 01, 1995
Filing Date:
July 26, 1988
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L27/092; H01L21/8238; H03K19/0948; (IPC1-7): H03K19/0948
Attorney, Agent or Firm:
Akira Kobiji (2 outside)