Title:
【発明の名称】混成集積回路用多層配線回路を有するハーメチックパッケージ構造体およびその製造方法
Document Type and Number:
Japanese Patent JPH07112101
Kind Code:
B2
Abstract:
PURPOSE:To improve integration and to reduce the size by laminating ceramic substrates having standard punched pattern, thereby forming a hybrid integrated circuit integrating a multi-layered wiring board and a hermetic package. CONSTITUTION:Longitudinal scribe lines 8 and lateral scribe lines 9 are made in a baked alumina substrate and through-holes 10 are formed on the lines, thus forming a substrate 111. A capacitor punching section 31, an IC bare chip punching section 41 and a thick film resistor punching section 71 are formed through laser machining in the substrate 111, thus obtaining substrates 112-114. Thick film circuits and thick film resistors 7 are printed on the substrates 111-114 and baked followed by printing of glass adhesive, then the substrates are laminated and baked to produce a multi-layered wiring board 1. A capacitor 3 and an IC bare chip 2 are mounted on the punched sections of the board 1 and the punched section associated with the IC bare chip is air-tightly sealed with a lid 4. In case of QFP type, a lead 6 is soldered to the substrate.
Inventors:
Kotaro Nose
Application Number:
JP30000388A
Publication Date:
November 29, 1995
Filing Date:
November 28, 1988
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
H05K1/18; H01L23/52; H05K3/46; H05K1/03; H05K1/16; H05K3/00; (IPC1-7): H05K1/18; H01L23/52; H05K3/46
Domestic Patent References:
| JP509757A | ||||
| JP6457653A |
Attorney, Agent or Firm:
Mikio Nakajima
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